Fractional frequency division is a technique for producing an output signal of desired frequency by dividing an input signal of known and preferably regulated frequency "f" by a number "k" to generate an output signal of lower, desired frequency f/k. In the art, circuits incorporating this frequency division technique are known. The divider "k" can be either an integer division of the input signal frequency or can be any rational number. However, difficulties arise when the frequency of the output signal, i.e. the quotient, does not correspond to an integer subdivision of the frequency of the input signal. Such difficulties can include significant timing jitter or phase noise.
U.S. Pat. No. 3,603,773--Carlstein discloses a variable pulse generator for generating, from a fixed frequency source, a train of pulses having a frequency proportional to an input digital number. First and second registers are described, wherein a number stored in the first register is continuously added to a running total in the second register, i.e., a phase accumulator. The addition operation occurs at a frequency equal to the fixed frequency. A carry output from the second register to a pulse shaper is said to provide a variable frequency output, the frequency of which is determined by the magnitude of the number stored in the first register. When no variable time delay circuit or method is used in combination with the phase accumulator, as in the Carlstein device, a maximum timing jitter of one input clock period can occur and a timing jitter of one-half clock period is common.
Attempts have been made to provide fractional frequency synthesizers which utilized rational numbers but yet exhibit reduced timing jitter. U.S. Pat. No. 3,976,945--Cox discloses a frequency synthesizer incorporating a modulo-n counter, an accumulator, a cycle swallower and a programmable delay generator. It should be noted that the rational number (divisor) used in frequency synthesis can include an integer value portion and a fractional value portion. In Cox, the integer value portion is said to be applied to the modulo-n counter as the value "n" and the fractional value portion is set in the accumulator and added to a "running total" for each pulse of the input digital clock signal. The mudulo-n counter generates a trigger signal every "n" pulses of the input signal which trigger signal is provided to the programmable delay generator. The programmable delay generator generates an output signal for every trigger signal, which output signal is delayed in relation to the running total then present in the accumulator. Whenever the running total in the accumulator exceeds 1.0, a signal from the carry output of the accumulator is sent to the cycle swallower. Upon receipt of the carry signal, the cycle swallower swallows one pulse of the input signal, i.e. one input pulse is not provided to the modulo-n counter.
U.S. Pat. No. 4,231,104--St. Clair discloses a frequency synthesizer incorporating multiple memories, an adder, a counter and a delay line element. Operation is described in terms of clock period instead of frequency. Two memory devices are provided for separate storage of the integer value and fractional value portions of the rational number by which the period of the master clock signal is to be divided. An adder device generates a running total, wherein the total is incremented by the fractional value portion for each output of the counter, i.e. each time the counter counts a number of clock periods equal to the integer value portion. For every output of the counter, the delay line element delays the output signal by an amount equal to the running total. Whenever the running total in the adder exceeds 1.0, the counter is inhibited from counting for one count or one period of the master clock signal.
Unfortunately, these attempts to reduce timing jitter will still exhibit inherent timing jitter error equal to a maximum of Tc/2.sup.M+1 ; where Tc is the input clock period and M is the number of bits used to generate the variable delay. Moreover, use of counter, pulse swallower and delay line circuits adds to the complexity of those frequency synthesizers resulting in increased manufacturing costs and increased probability of jitter and noise problems. It should also be noted that digital delay line devices are relatively expensive.
Other techniques have been attempted such as the phase lock loop synthesizer. Ulrich Rhode, Digital PLL Frequency Synthesis, Prentice-Hall 1983 p. 110. However, this method represents a compromise between frequency range, number of frequencies available, phase noise and complexity. In order to achieve a large number of possible synthesized frequencies with good phase noise and lock-in time, considerable complexity is required. In other words to achieve high frequency resolution and also to be able to quickly switch to a new frequency using PLL techniques, a device of considerable complexity is required.
Direct digital synthesis is still another method of generating or synthesizing a selected frequency. Robert J. Zaurel, "A Direct Digital Synthesis VFO"; Ham Radio, Sep. 1988, p. 10-17. This technique also uses a phase accumulator but provides the accumulator output to a ROM (Read-Only-Memory) look-up table instead of a variable time delay. The ROM is the limiting factor in the speed and cost of the circuit. Use of the ROM lookup table also produces a source of quantization error.
Consequently, a need still exists for a frequency synthesizer which can quickly switch from one frequency to another and which exhibits significantly less timing jitter or phase noise than prior devices.